FPGA Based Accelerators for Financial Applications by Christian Schryver

Author:Christian Schryver
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

2.The Programmable Systems (PS), a complete sub-system with ARM CPU cores and different peripherals.

The PS contains the following items: An ARM Cortex MPCore-A9 dual core processing engine which also contains NEON Single Instruction Multiple Data (SIMD) units. Each ARM core has its own L1 data and instruction caches. Each cache block has a size of 32 KB.

One L2 cache with the size of 512 KB which is shared between two CPU cores. The ARM PL310 cache controller is used for implementation of this unit.

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